A cache is a memory that is functionally located between a data processor and its main memory. The cache is smaller but faster than the main memory. A cache memory decreases the effective access time of a memory system by storing copies of data that are also present in main memory. Here, the term "data" may include both program instructions and the data that they manipulate. Because of its size, the cache cannot hold copies of all of the main memory contents. When the processor performs a memory read operation, the cache tests to see if it contains the referand. If so, the cache will provide it to the processor, and no main memory access will occur. If the referenced data is not present in the cache, main memory will be accessed. References which find their target in the cache are called cache hits. All other memory references are called cache misses.
A main memory address consists of two fields. The higher order bits are called the tag field, while the remaining lower order bits are the index field. The cache uses a tag memory, separate from its data memory, to remember the tag fields of the addresses of the main memory contents that it presently holds. When the processor performs a memory access, the index field of the address is used to address the tag memory. The output data from the tag memory is then compared bit by bit with the tag field of the main memory address. If the two fields are identical, a hit has occurred, and the corresponding data will be supplied to the processor. If the fields are not identical, it is a miss, and main memory must be accessed.
If contents of the tag memory were to become corrupted, memory accesses that should miss may actually hit. This would result in incorrect data being supplied to the processor, a dangerous occurrence. Therefore, it is desirable that some method of error checking be performed over the tag fields when they are output from the tag memory. It is common to use a single parity bit over each word in the tag memory. If bad parity is detected when tag memory is read, a miss condition is forced. In the prior art, a parity check on the tag information is performed after the tag information is read from tag memory. This serial action slows the cache memory. It would be beneficial if this serial action could be replaced by a faster arrangement.